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- W4223502081 abstract "Next generation 3D VNAND Flash memory device with 176 Word-line (WL) layer has been successfully built. The Cell-Over-Peripheral (COP) architecture was used, which reduced tR (Read Latency) by 11% and tPROG (Program Latency) by 20%, respectively. The bit density has been enhanced by 70% over our previous device (6th generation) thanks to cell volume scaling and COP architecture. To create this new device, double stack process was successfully merged for higher bit density. In addition, the channel hole profile was greatly improved using the double stack method. As a result, compared to our earlier product, we were able to attain superior cell operation characteristics. The technology used in the 7th generation 3D VNAND device, as well as our ongoing efforts to expand it to QLC devices and their results will be discussed in this paper." @default.
- W4223502081 created "2022-04-15" @default.
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- W4223502081 date "2022-02-06" @default.
- W4223502081 modified "2023-10-12" @default.
- W4223502081 title "Development of 7th generation 3D VNAND Flash Product with COP structure for Growing Demand in Storage Market" @default.
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- W4223502081 doi "https://doi.org/10.1109/iceic54506.2022.9748730" @default.
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