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- W4226305107 abstract "This brief presents the modeling and design of a static current-mode logic, divide-by-2 frequency divider for mm-wave frequency synthesis. An optimized design procedure based on the <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex-math notation=LaTeX>$RC$ </tex-math></inline-formula> delay model and insights into the nonlinear mixing conversion gain of the injection-locking model are presented and leveraged towards the design of an inductor-less 28-nm CMOS prototype that achieves 72 GHz maximum input frequency and power-delay product of 21.5 fJ. Performance can be tuned to 66 GHz and 16.9 fJ, respectively, via lowering the supply voltage. In addition to standalone measurements with an off-chip input signal, a fundamental-frequency dual-core voltage-controlled oscillator provides on-chip and realistic input signal generation." @default.
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- W4226305107 date "2022-06-01" @default.
- W4226305107 modified "2023-09-26" @default.
- W4226305107 title "Design of an Inductor-less 72-GHz 2:1 CMOS CML Frequency Divider with Dual-Core VCO" @default.
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- W4226305107 doi "https://doi.org/10.1109/tcsii.2022.3167791" @default.
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