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- W4233307210 abstract "A novel serial-in parallel-out finite field multiplier using redundant representation is proposed. It is shown that the proposed architecture has either a significantly lower complexity and comparable critical path delay or a significantly smaller critical path delay and comparable complexity in comparison to the previously proposed architectures using the same representation. For the class of fields where there exists a type I optimal normal basis, the proposed multiplier compares favorably to the normal basis multipliers. A digit-level version for the new multiplier is also presented in this paper." @default.
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- W4233307210 date "2008-01-01" @default.
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- W4233307210 title "A New Finite-Field Multiplier Using Redundant Representation" @default.
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- W4233307210 doi "https://doi.org/10.1109/tc.2007.70834" @default.
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