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- W4234830159 abstract "The increasingly popular sub-threshold design is strongly calling for EDA support to estimate noise margins, minimum functional supply voltage, as well as the functional yield. In this paper, we propose a fast, accurate and statistical approach to accomplish these goals. First, we derive close-form functions based on a new equivalent resistance model which enables the fast estimation of noise margins of individual cells at the gate-level. Second, we propose to calculate and propagate the noise margin information with an affine arithmetic model that takes into account process variations and correspondent inter-cell correlations. Experiments with ISCAS benchmarks have shown that the new approach has an accuracy of 98.5% w.r.t. transistor-level Monte Carlo simulations. The running time per input vector of the new approach only needs a few seconds, in contrast to the many hours required by transistor-level DC Monte-Carlo simulations. To the best of our knowledge, we are the first to provide a fast, accurate and statistical methodology other than Monte-Carlo simulation for the noise margin estimation of sub-threshold combinational circuits." @default.
- W4234830159 created "2022-05-12" @default.
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- W4234830159 date "2008-01-01" @default.
- W4234830159 modified "2023-09-29" @default.
- W4234830159 title "Statistical noise margin estimation for sub-threshold combinational circuits" @default.
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- W4234830159 doi "https://doi.org/10.1109/aspdac.2008.4483935" @default.
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