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- W4235839976 abstract "This paper presents a systematic comparison between two different implementations of a distributed network on chip: fully asynchronous and multi-synchronous. The NoC architecture has been designed to be used in a globally asynchronous locally synchronous clusterized multi processors system on chip. The 5 relevant parameters are silicon area, network saturation threshold, communication throughput, packet latency and power consumption. Both architectures have been physically implemented and simulated by SystemC/VHDL co-simulation. The electrical parameters have also been evaluated by post layout SPICE simulation for a 90nm CMOS fabrication process, taking into account the long wire effects" @default.
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- W4235839976 date "2007-04-01" @default.
- W4235839976 modified "2023-09-27" @default.
- W4235839976 title "Systematic Comparison between the Asynchronous and the Multi-Synchronous Implementations of a Network on Chip Architecture" @default.
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- W4235839976 doi "https://doi.org/10.1109/date.2007.364439" @default.
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