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• W4236677774 abstract "In spite of the mature cell structure, the memory controller architecture of Multi-level cell (MLC) NAND Flash memories is evolving fast in an attempt to improve the uncorrected/miscorrected bit error rate (UBER) and to provide a more flexible usage model where the performance-reliability trade-off point can be adjusted at runtime. However, optimization techniques in the memory controller architecture cannot avoid a strict trade-off between UBER and read throughput. In this paper, we show that co-optimizing ECC architecture configuration in the memory controller with program algorithm selection at the technology layer, a more flexible memory sub-system arises, which is capable of unprecedented trade-offs points between performance and reliability." @default.
• W4236677774 created "2022-05-12" @default.
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• W4236677774 date "2012-03-01" @default.
• W4236677774 modified "2023-10-02" @default.
• W4236677774 title "A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories" @default.
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• W4236677774 doi "https://doi.org/10.1109/date.2012.6176622" @default.
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