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- W4238487776 abstract "This paper presents a high-level design methodology applied on an SoC using SystemC. The topic will emphasize on high-level design approach for intensive architecture exploration and verifying cycle accurate SystemC models comparative to real Verilog RTL models. Unlike many high-level designs, we started the project with working Verilog RTL models in hands, which we later compared our SystemC models to real Verilog RTL models. Moreover, we were able to use the on-chip test board performance simulation data to verify our SystemC-based platform. This paper illustrates that in high-level design, we could have the same accuracy as RTL models but achieve over one hundred times faster simulation speed than that of RTL's. The main topic of the paper will be on architecture exploration in search of performance degradation in source." @default.
- W4238487776 created "2022-05-12" @default.
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- W4238487776 date "2007-11-01" @default.
- W4238487776 modified "2023-09-29" @default.
- W4238487776 title "Architecture Exploration for Performance Improvement of SoC Chip Based on AMBA System" @default.
- W4238487776 doi "https://doi.org/10.1109/iccit.2007.4420347" @default.
- W4238487776 hasPublicationYear "2007" @default.
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