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- W4238558133 abstract "We present a 22.5-27.7-GHz fast-lock low-phase-noise bang-bang digital phase-locked loop (PLL) for mm-wave communication. The fast lock is achieved with the help of the proposed gear-shift algorithm, scaling up the PLL bandwidth for faster settling, and orderly reducing it for jitter performance. A digitally controlled oscillator (DCO), based on transformer feedback with a tunable source-bridged capacitor, exhibits low phase noise (PN) over a wide tuning range (FoM of -184 dBc/Hz and FoMT of -191 dBc/Hz). The PLL occupies 0.09-mm2 core area and exhibits 220-fs RMS jitter while consuming 25 mW, giving FoMRMS of -239 dB. Its settling time improves from 780 to 45 μs with our gear-shift algorithm. For 60-GHz communication, with a frequency multiplication factor of 2.5, this PLL covers all six channel frequencies of IEEE-802.11ad and is capable of supporting 128 QAM and beyond." @default.
- W4238558133 created "2022-05-12" @default.
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- W4238558133 date "2019-09-01" @default.
- W4238558133 modified "2023-10-01" @default.
- W4238558133 title "A 22.5–27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication With 220-fs RMS Jitter" @default.
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- W4238558133 doi "https://doi.org/10.1109/lssc.2019.2935570" @default.
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