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- W4240302012 abstract "The emerging design requirements with the FinFET technology, along with traditional geometrical constraints, make the FinFET-based analog placement even more challenging. Previous works can handle only partial FinFET-induced design constraints because some new constraints are intrinsically different from the traditional ones; as a result, directly extending previous methods to handle FinFET-induced constraints would incur solution quality degradation and runtime overhead. To remedy these disadvantages, we present a new hybrid graph (meshed tree) representation of a window mesh and CB-trees (namely, WB-trees) and a new placement flow with effective and efficient schemes to simultaneously handle FinFET-based design constraints and traditional ones. Experimental results based on industrial designs with various constraints show that our placer outperforms published works in both solution quality and runtime." @default.
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- W4240302012 date "2018-06-01" @default.
- W4240302012 modified "2023-10-16" @default.
- W4240302012 title "WB-Trees: A Meshed Tree Representation for FinFET Analog Layout Designs" @default.
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- W4240302012 doi "https://doi.org/10.1109/dac.2018.8465840" @default.
- W4240302012 hasPublicationYear "2018" @default.
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