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- W4241448073 abstract "This work presents a small-size 10b 10MS/s SAR ADC with an integrated passive anti-aliasing filter, consuming 39.2μW overall in 65nm CMOS. A new DAC layout technique is used to achieve better matching without using area-expensive unit elements, resulting in a minimum ADC chip area of 36 × 36μm while achieving 9.18b ENOB. A 4× time-interleaved 15-tap passive FIR filter is implemented with switched-capacitors, realizing >42dB out-of-band rejection and 4× decimation, while occupying only 53×90μm. Both components are not only small in chip area, but also offer competitive power-efficiency." @default.
- W4241448073 created "2022-05-12" @default.
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- W4241448073 date "2018-04-01" @default.
- W4241448073 modified "2023-09-27" @default.
- W4241448073 title "A 0.0013mm2 10b 10MS/s SAR ADC with a 0.0048mm2 42dB-rejection passive FIR filter" @default.
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- W4241448073 doi "https://doi.org/10.1109/cicc.2018.8357059" @default.
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