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- W4242220859 abstract "Leakage effects in deep sub-0.1μm CMOS technologies are of critical concern to designers of high-performance integrated circuits. Recent estimates [1] of a 7.5x increase in leakage current per chip generation; along with several proposals for energy-efficient cache architectures that unfortunately do not address static leakage-energy issues [2], [3], [4], have heightened concerns over the functionality and stability of future high-performance SRAM cache designs. Each of these future technology generations, in addition to having increased short-channel effects (SCEs) will now also suffer from gate leakage currents across physically and electrically thin (1.5nm) SiO2 gate dielectrics. In this paper we demonstrate the limits of this scaling on the operational behavior of on-chip SRAM cache designs, and briefly discuss the impact of these results on high-performance memory architectures." @default.
- W4242220859 created "2022-05-12" @default.
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- W4242220859 date "2002-01-01" @default.
- W4242220859 modified "2023-09-27" @default.
- W4242220859 title "Design limitations in deep sub-0.1μm CMOS SRAM" @default.
- W4242220859 doi "https://doi.org/10.1145/505324.505327" @default.
- W4242220859 hasPublicationYear "2002" @default.
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