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• W4242759096 abstract "Take a multicore Digital Signal Processor (DSP) chip designed for cellular base stations and radio network controllers, add floating-point capabilities to support 4G networks, and out of thin air a HPC engine is born. The potential for HPC is clear: It promises 128 GFLOPS (single precision) for 10 Watts; It is used in millions of network related devices and hence benefits from economies of scale; It should be simpler to program than a GPU. Simply put, it is fast, green, and cheap. But is it easy to use? In this paper, we show how this potential can be applied to general-purpose high performance computing, more specifically to dense matrix computations, without major changes in existing codes and methodologies, and with excellent performance and power consumption numbers." @default.
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• W4242759096 date "2012-11-01" @default.
• W4242759096 modified "2023-10-18" @default.
• W4242759096 title "Unleashing the high-performance and low-power of multi-core DSPs for general-purpose HPC" @default.
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• W4242759096 doi "https://doi.org/10.1109/sc.2012.109" @default.
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