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- W4243397932 abstract "This chapter begins with normally-off computing, which achieves sufficiently high performance at minimum power consumption. It then introduces normally-off central processing units (CPUs) and c-axis-aligned crystalline indium-gallium-zinc oxide (CAAC-IGZO) cache memory based on CAAC-IGZO field-effect transistors (FETs). The chapter explains the operation of the CPU using backup flip-flops (FF) and discusses cache memories with static random access memory (SRAM) based on CAAC-IGZO FETs. It also introduces the hybrid SRAM that was fabricated from CAAC-IGZO FETs with extremely low off-state current. The CPU is synchronized with an external clock signal output. The data path has a register file and an arithmetic logic unit (ALU). The chapter explains a 32-bit normally-off CPU with an ARM architecture using Type-B backup FFs. It summarizes the structures and performances of various power-gating technologies. The prototype CAAC-IGZO SRAM shows superior frequency characteristics in normal operation and dramatically reduced backup and restoration energies." @default.
- W4243397932 created "2022-05-12" @default.
- W4243397932 date "2016-10-28" @default.
- W4243397932 modified "2023-10-14" @default.
- W4243397932 title "CPU" @default.
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- W4243397932 doi "https://doi.org/10.1002/9781119247418.ch5" @default.
- W4243397932 hasPublicationYear "2016" @default.
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