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- W4243880023 abstract "In the past, symbolic trajectory evaluation (STE) was shown to be effective for verifying individual array blocks. However, when applying STE to verify multiple array blocks together as a single system, the run-time OBDD sizes would often blow up. In this paper, we propose using a dual-rail symbolic simulation scheme to facilitate the application of STE proof methodology for verifying array systems. The proposed scheme implicitly partitions a given design into control domain and datapath domain, and symbolic simulation is carried out on both domains. With this scheme, the run-time OBDD sizes during the symbolic simulation for each domain can be limited. We demonstrate the effectiveness of our approach by verifying the memory management unit (MMU) in Motorola high-performance microprocessors. The verification of MMU as a whole was not possible before because of the OBDD size blow-up problem when an ordinary symbolic simulator was used in the STE proof process." @default.
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- W4243880023 date "2003-08-27" @default.
- W4243880023 modified "2023-09-24" @default.
- W4243880023 title "Enhanced symbolic simulation for efficient verification of embedded array systems" @default.
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- W4243880023 doi "https://doi.org/10.1109/aspdac.2003.1195032" @default.
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