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- W4245698512 abstract "Modern Convolutional Neural Networks (CNNs) are computation and memory intensive. Thus it is crucial to develop hardware accelerators to achieve high performance as well as power/energy-efficiency on resource limited embedded systems. DRAM-based CNN accelerators exhibit great potentials but face inference accuracy and area overhead challenges.In this paper, we propose DrAcc, a novel DRAM-based processing-in-memory CNN accelerator. DrAcc achieves high inference accuracy by implementing a ternary weight network using in-DRAM bit operation with simple enhancements. The data partition and mapping strategies can be flexibly configured for the best trade-off among performance, power and energy consumption, and DRAM data reuse factors. Our experimental results show that DrAcc achieves 84.8 FPS (frame per second) at 2W and 2.9× power efficiency improvement over the process-near-memory design." @default.
- W4245698512 created "2022-05-12" @default.
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- W4245698512 date "2018-06-01" @default.
- W4245698512 modified "2023-10-01" @default.
- W4245698512 title "DrAcc: a DRAM based Accelerator for Accurate CNN Inference" @default.
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- W4245698512 doi "https://doi.org/10.1109/dac.2018.8465866" @default.
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