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- W4246393721 abstract "The capability of performing architectural exploration has become essential for embedded microprocessor design in System-On-Chip. While many retargetable instruction set (ISA) simulators have been reported, the more relevant micro-architecture simulators, which are capable of modeling the detailed machine features such as cache organization, branch prediction and out-of-order scheduler, have not be equipped with retargetability. In this paper, we propose a new methodology that can generate completed micro-architecture simulators from the abstract ISA and the application binary interface (ABI) specification. We demonstrate our methodology by the development of a tool that can automatically port the SimpleScalar toolset, the de facto standard for micro-architecture simulation, to any processor." @default.
- W4246393721 created "2022-05-12" @default.
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- W4246393721 date "2003-01-01" @default.
- W4246393721 modified "2023-10-16" @default.
- W4246393721 title "A retargetable micro-architecture simulator" @default.
- W4246393721 doi "https://doi.org/10.1145/776024.776025" @default.
- W4246393721 hasPublicationYear "2003" @default.
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