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- W4246440101 abstract "In this paper, we propose a logic optimization technique for FPGAs (Field Programmable Gate Arrays). Generally, logic blocks of FPGAs are often regarded as ones each of which can realize only one k-input function. Widely used logic blocks, however, consist of cells that can realize one h-input function, and these blocks can realize a k-input function by the combination of cell output functions. Due to such a structure, there are the following two cases for functions realized by one block. (a) One k(>h)-input function. (b) Two (or more) independent h-input functions. Almost all CAD tools use only (a). Recently, the use of (b) has been reported. In addition, we propose the following case. (c) One k (> h)-input function and one (or more) h-input function used to realize the k-input function. To use (c), we will develop procedures to produce circuits with reduced numbers of FPGA blocks. Our method tries to merge two blocks into one block to realize reduction of the number of blocks. As realization of mutually related k-input and h-input function is time-consuming, we will focus on a special class of k-input functions for which h-input functions can be specified arbitrary. To achieve further block integration, we use permissible functions and error compensation procedures due to their powerful conversion capability. The effectiveness of the proposed methods is shown by MCNC benchmarks. Experimental results show that the number of blocks related to chip area closely is 37% reduced on average. © 1999 Scripta Technica, Syst Comp Jpn, 30(11): 12–21, 1999" @default.
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- W4246440101 date "1999-10-01" @default.
- W4246440101 modified "2023-09-27" @default.
- W4246440101 title "FPGA circuit optimization using block integration based on multiple output capability" @default.
- W4246440101 doi "https://doi.org/10.1002/(sici)1520-684x(199910)30:11<12::aid-scj2>3.3.co;2-d" @default.
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