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- W4248172804 abstract "In a shared-memory based tiled many-core system-on-chip architecture, memory accesses present a huge performance bottleneck in terms of access latency as well as bandwidth requirements. The best practice approach to address this issue is to provide a multi-level cache hierarchy and a suitable cache-coherency mechanism. This paper presents a method to increase the memory access performance in distributed-directory-coherency-protocol based tiled many-core systems. The proposed method introduces an alternate design for the system-wide shared last-level caches (LLC) placed between the memory and the node private caches (NPC). The proposed system-wide shared LLC layer is distributed over the entire network and it interacts with the home directories of specific cache lines. Results from simulating SPEC2000 benchmark applications executed on a SystemC model of the proposed design show a minimum performance improvement of 20-25% when compared to a model without the shared cache layer at the expense of an additional 2% of the total cache memory space (NPC + LLC memory). In addition, the proposed design shows a minimum 7-15% and an average 14-15% improvement in performance in comparison to centralized system-wide shared LLC of equivalent size and dynamic mapped distributed LLC of equivalent size respectively." @default.
- W4248172804 created "2022-05-12" @default.
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- W4248172804 date "2014-01-01" @default.
- W4248172804 modified "2023-10-16" @default.
- W4248172804 title "Distributed cooperative shared last-level caching in tiled multiprocessor system on chip" @default.
- W4248172804 doi "https://doi.org/10.7873/date2014.096" @default.
- W4248172804 hasPublicationYear "2014" @default.
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