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- W4251100134 abstract "Secure processors enable new applications by ensuring private and authentic program execution even in the face of physical attack. In this paper, we present the AEGIS secure processor architecture, and evaluate its RTL implementation on FPGAs. By using physical random functions, we propose a new way of reliably protecting and sharing secrets that is more secure than existing solutions based on non-volatile memory. Our architecture gives applications the flexibility of trusting and protecting only a portion of a given process, unlike prior proposals which require a process to be protected in entirety. We also put forward a specific model of how secure applications can be programmed in a high-level language and compiled to run on our system. Finally, we evaluate a fully functional FPGA implementation of our processor, assess the implementation tradeoffs, compare performance, and demonstrate the benefits of partially protecting a program." @default.
- W4251100134 created "2022-05-12" @default.
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- W4251100134 date "2005-07-28" @default.
- W4251100134 modified "2023-09-28" @default.
- W4251100134 title "Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions" @default.
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- W4251100134 doi "https://doi.org/10.1109/isca.2005.22" @default.
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