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- W4255786265 abstract "Because of the progress in dual gate Silicon on Insulator (DG-SOI) metal oxide semiconductor field effect transistors (MOSFETs), new directions have been taken to move in “surround” gate or “wrap-around” gate structures. Concepts of surround gates, wrap-around gates and non-planar dual gates were all different strategies on constructing the non-planar MOSFET into narrow-width silicon pillars leaving the wafer surface to form the 3-D MOSFET structures. The SOI FinFET structure forms a parallelepiped surrounded by isolation material below and above the conducting region, and the thermal sinks formed by the boundary conditions. For electrostatic discharge (ESD) phenomena, there are two issues. The first issue is how the current distributes between multiple parallel FinFET devices. A second issue is the relative width of a current constriction to the effective fin width and height. The chapter shows ESD failures and transmission line pulse measurements in FinFET structures." @default.
- W4255786265 created "2022-05-12" @default.
- W4255786265 date "2021-03-26" @default.
- W4255786265 modified "2023-09-23" @default.
- W4255786265 title "ESD in Bulk and SOI FINFET" @default.
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- W4255786265 doi "https://doi.org/10.1002/9781119233091.ch23" @default.
- W4255786265 hasPublicationYear "2021" @default.
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