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- W4256706039 abstract "SAR ADC has a moderate speed, Low area and low cost compared to other ADC implementations. The accuracy expected from a commercial SAR ADC is very high and research has been going on for many years to improve the accuracy. The Linearity of the data converters is the key for accuracy. The Integral nonlinearity and differential nonlinearity errors of data converters are governed by the matching of the unit capacitors/resistors with in capacitor/resistor array. Layout of these arrays can add significant parasitics affecting the nonlinearity of data converters. This paper presents a layout technique to reduce the impact of the parastics on data converter’s nonlinearity." @default.
- W4256706039 created "2022-05-12" @default.
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- W4256706039 date "2019-07-30" @default.
- W4256706039 modified "2023-10-17" @default.
- W4256706039 title "A Layout Technique to Reduce the Impact of Parasitic Capacitors Within A Capacitor Array on the Nonlinearity of Data Converters" @default.
- W4256706039 doi "https://doi.org/10.35940/ijitee.i7634.078919" @default.
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