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- W4285058210 abstract "This letter presents a fully integrated frequency doubler in the TSMC 28-nm CMOS technology. MOS transistor capacitor neutralization is introduced in the differential driving amplifier, which shows better robustness than MOM capacitor neutralization under PVT variations. Besides, a stacked transformer-based balun is designed to achieve good balance performance. The effect of dummy metal on the performance of the proposed balun is also discussed. The measured results show that the 3-dB bandwidth is 25 GHz (208–233 GHz) and the peak power-added efficiency is 1.1% with a dc power consumption of 26.4 mW at 222 GHz. The peak conversion gain is −7.2 dB and the variation in conversion gain is less than 1 dB within −7- to 1-dBm input power range. Moreover, the chip size is <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex-math notation=LaTeX>$492times 412,,mu text{m}^{2}$ </tex-math></inline-formula> , including GSG and DC pads." @default.
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- W4285058210 date "2022-11-01" @default.
- W4285058210 modified "2023-10-16" @default.
- W4285058210 title "A 208–233-GHz Frequency Doubler With 1.1% Power-Added Efficiency in 28-nm CMOS" @default.
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- W4285058210 doi "https://doi.org/10.1109/lmwc.2022.3180082" @default.
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