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- W4285112330 abstract "This brief presents two low consumption balanced front-end amplifiers designed in 65nm PD-SOI CMOS technology dedicated to low output power 60 GHz short-range wireless applications. For both designs, a resistive feedback neutralized common source differential pair architecture is used with 90° twisted hybrid couplers which allows power combining in addition to an improved robustness against load variations shown by load-pull experimental results. A specific design approach is used to reduce power consumption and limit the output power level. The one-stage amplifier exhibits a gain of 5.43 dB, an OCP1dB of 4.5 dBm, a saturated power superior to 6.33 dBm and a peak PAE of 8.6 % for a total power consumption of solely 14 mW and an active area of 0.17 mm2. The three-stage amplifier exhibits a gain of 21 dB, an OCP1dB of 3.7 dBm, a <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex-math notation=LaTeX>${mathbf {P}}_{mathbf {sat}}$ </tex-math></inline-formula> of 7 dBm and a peak PAE of 8.4 % under a total power consumption of only 42 mW and an active area of 0.3 mm2. All the reported performances are obtained at 60 GHz from a 1V supply voltage." @default.
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- W4285112330 date "2022-10-01" @default.
- W4285112330 modified "2023-09-23" @default.
- W4285112330 title "Low Consumption Balanced Front-End Amplifiers Robust to Load Variations in 65nm PD-SOI CMOS Technology for 60 GHz Short-Range Wireless Applications" @default.
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- W4285112330 doi "https://doi.org/10.1109/tcsii.2022.3185552" @default.
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