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- W4285209791 abstract "A fast-settling phase-locked loop (PLL) adopting the cycle-slipping-elimination phase frequency detector and charge pump (CSE-PFDCP) is presented. The CSE-PFDCP solves the cycle-slipping problem in a conventional non-linear PFDCP (NL-PFDCP), which accelerates the settling speed of the PLL. In addition, the metastability problem of the proposed cycle-slipping-elimination technology is analyzed in this brief. The proposed fast-settling PLL is fabricated in a 180 nm CMOS process with core area of 0.38 mm2. The frequency range of the PLL prototype is 2.1-2.6 GHz. Using the proposed CSE-PFDCP, the settling time is less than 6 <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex-math notation=LaTeX>$mu text{s}$ </tex-math></inline-formula> when the PLL frequency jump is 480 MHz, and the PLL settling speed is increased by 171%." @default.
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- W4285209791 date "2022-10-01" @default.
- W4285209791 modified "2023-09-30" @default.
- W4285209791 title "A Fast-Settling Phase-Locked Loop Utilizing Cycle-Slipping-Elimination PFDCP" @default.
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- W4285209791 doi "https://doi.org/10.1109/tcsii.2022.3177763" @default.
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