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- W4285259390 abstract "In general, length-matching constraint in single-layer bus routing can be expected to be satisfied for timing requirement in high-performance PCBs. In this paper, given a set of non-crossing buses inside a routing plane with some circuit components and rectangular obstacles, an efficient algorithm can be proposed for single-layer obstacle-aware multiple-bus routing considering simultaneous escape length in bus-oriented PCB routing. Firstly, based on the obstacle-aware partition of the available area inside a routing plane and the construction of a directed capacity-constrained path graph, the obstacle-aware flow-based shortest paths of the routing nets inside the given buses can be constructed to minimize the number of the used routing grids. Furthermore, based on the obstacle-aware flow-based shortest paths of the routing nets inside the given buses and the consideration of the simultaneous escape lengths on the given buses, the detouring-paths can be further inserted onto the shortest paths of the routing nets inside the given buses to minimize the maximum skew of the routed buses with satisfying the length-matching constraints on the given buses. Compared with the iterative single-bus routing process using Yan’s routing algorithm, the experimental results show that our proposed algorithm uses less CPU time to increase 10.7% of the number of the total routed buses and 13.4% of the number of the total routed nets inside the given buses for 8 tested examples on the average. In addition, the final maximum skew of the routed buses can be reduced from 14.25 to 1.38 for 8 tested examples on the average." @default.
- W4285259390 created "2022-07-14" @default.
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- W4285259390 date "2022-01-01" @default.
- W4285259390 modified "2023-10-16" @default.
- W4285259390 title "Single-Layer Obstacle-Aware Multiple-Bus Routing Considering Simultaneous Escape Length" @default.
- W4285259390 doi "https://doi.org/10.1109/tcpmt.2022.3175069" @default.
- W4285259390 hasPublicationYear "2022" @default.
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