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• W4285503888 abstract "Data movements between different levels of the memory hierarchy (I/O-transitions, or simply I/O s) are a critical performance bottleneck in modern computing. Therefore it is a problem of high practical relevance to find algorithms that use a minimal number of I/O s. We present a cache-oblivious sparse matrix-sparse matrix multiplication algorithm that uses a worst-case number of I/O s that matches a previously established lower bound for this problem (0 (N2/B.M) read-I/Os and 0 (N2/B) write-I/Os, where <tex xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>$N$</tex> is the size of the problem instance, <tex xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>$M$</tex> is the size of the fast memory and <tex xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>$B$</tex> is the size of the cache lines). When the output does not need to be stored, also the number of write-I/Os can be reduced to 0 (N2/B.M). This improves the worst-case I/O-complexity of the previously best known algorithm for this problem (which is cache-aware) by a logarithmic multiplicative factor. Compared to other cache-oblivious algorithms our algorithm improves the worst-case number of I/Os by a multiplicative factor of Θ(M. N). We show how the algorithm can be applied to produce the first I/O-efficient solution for the sparse 2- vs 3-diameter problem on sparse directed graphs." @default.
• W4285503888 created "2022-07-15" @default.
• W4285503888 creator A5026990786 @default.
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• W4285503888 date "2022-05-01" @default.
• W4285503888 modified "2023-09-26" @default.
• W4285503888 title "I/O-Optimal Cache-Oblivious Sparse Matrix-Sparse Matrix Multiplication" @default.
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• W4285503888 doi "https://doi.org/10.1109/ipdps53621.2022.00013" @default.
• W4285503888 hasPublicationYear "2022" @default.
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