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- W4286571776 abstract "An energy-efficient high bandwidth array design using 0.0300-μm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> high performance SRAM bitcell on Intel 4 CMOS technology is presented. By employing a unique combination of design techniques, the proposed 6T SRAM array design demonstrates >80% access energy improvement over a conventional 4-way interleaved 6T SRAM array design and 30% macro density improvement compared to a hierarchical 8T SRAM design for high bandwidth memory applications." @default.
- W4286571776 created "2022-07-22" @default.
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- W4286571776 date "2022-06-12" @default.
- W4286571776 modified "2023-10-18" @default.
- W4286571776 title "Energy-Efficient High Bandwidth 6T SRAM Design on Intel 4 CMOS Technology" @default.
- W4286571776 doi "https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830148" @default.
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