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- W4286571821 abstract "A 12b 10GS/s 16-channel time-interleaved (TI) ADC with cascaded input buffers, 625MS/s voltage-current (V-I) pipelined SAR ADCs and a digital processing timing-skew background calibration is proposed. A prototype 10GS/s TI ADC in 5nm FinFET achieves 48dB SNDR at the Nyquist input with 625mW power consumption, leading to a FoM <inf xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>Walden</inf> of 305fJ/c-s." @default.
- W4286571821 created "2022-07-22" @default.
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- W4286571821 date "2022-06-12" @default.
- W4286571821 modified "2023-10-15" @default.
- W4286571821 title "A 12-bit 10GS/s 16-Channel Time-Interleaved ADC with a Digital Processing Timing-Skew Background Calibration in 5nm FinFET" @default.
- W4286571821 doi "https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830208" @default.
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