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- W4286571826 abstract "A 28nm embedded Flash memory presented in this paper maximizes memory operation efficiently while implementing an optimal size. The peripheral size was reduced by applying the temperature auto tracking assist circuit with Bidirectional and Series-Parallel Conversion (BSPC) charge pump technology, and the IP size was improved by implementing the maximum density per mat by enhancing the sensing margin using Source Line Floating (SLF) technology. Also, using Program Current Auto Control (PCAC) scheme, program operation efficiency was improved and characteristic deviation of bit cell was reduced. With the application of these technologies, 72 bits program and 144 bits read operation are supported, and chip size 2.367mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> is implemented based on 32Mbit density. This has the best competitiveness considering the area Mbit (13.48Mb/mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> ) and Cell efficiency (68.1%)." @default.
- W4286571826 created "2022-07-22" @default.
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- W4286571826 date "2022-06-12" @default.
- W4286571826 modified "2023-10-16" @default.
- W4286571826 title "A 32Mb Embedded Flash Memory based on 28nm with the best Cell Efficiency and Robust Design achievement featuring 13.48Mb/mm<sup>2</sup> at 0.85V" @default.
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- W4286571826 doi "https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830151" @default.
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