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• W4286571855 abstract "In our work we describe and demonstrate an alternative approach of integrating 1T-1C FeFET having separated transistor (1T) without modifying frontend CMOS technology and an additional gate-coupled ferroelectric (FE) capacitor (1C) embedded in the interconnect layers. Starting from the results of FE capacitor integration and 1T-1C single cell characterization this paper describes realization and results of a fully integrated 8 kbit memory array implementation." @default.
• W4286571855 created "2022-07-22" @default.
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• W4286571855 date "2022-06-12" @default.
• W4286571855 modified "2023-10-16" @default.
• W4286571855 title "Memory Array Demonstration of fully integrated 1T-1C FeFET concept with separated ferroelectric MFM device in interconnect layer" @default.
• W4286571855 cites W2885718248 @default.
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• W4286571855 doi "https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830141" @default.
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