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- W4286571882 abstract "In this work, we present the first ASIC implementation of CNN-based data detection channel for HDDs with 30.3% error rate reduction than the SOTA detection channel. Our chip demonstrates the first methodology of systematically embedding non-linear capacity into HDD read channel with the following features (1) a fully unrolled CNN with dedicated silicon for each convolution layer to produce fast sequential time series data detection at 200 Mbits/s, (2) in total 6 depthwise-separable convolution layers implemented with 2 types of systolic arrays and 100% PE utilization for continuous data flow and high pipelining, (3) integer-only convolutions for improved efficiency at 0.86nJ/bit and 3.99TOPS/W, and (4) pipelined (QReLU) to maintain low-precision feature maps and recover accuracy loss from model quantization." @default.
- W4286571882 created "2022-07-22" @default.
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- W4286571882 date "2022-06-12" @default.
- W4286571882 modified "2023-10-16" @default.
- W4286571882 title "Non-linear CNN-based Read Channel for Hard Disk Drive with 30% Error Rate Reduction and Sequential 200Mbits/second Throughput in 28nm CMOS" @default.
- W4286571882 cites W2061523149 @default.
- W4286571882 doi "https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830238" @default.
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