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- W4286571896 abstract "This work presents a hybrid time and voltage domain ADC that uses a single high-speed voltage-to-time converter (VTC) as a sampling buffer for interleaved SAR ADCs to enhance bandwidth and remove timing skew mismatch. Time-domain encoding also allows a low-power 3b assist TDC to enhance SAR speed with minimal calibration. At 3.8 GS/s, the 0.0045 mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> 22nm FinFET prototype with 13 GHz ERBW consumes 6.0 mW with a Nyquist SNDR of 38 dB for 24.4 fJ/step FoM." @default.
- W4286571896 created "2022-07-22" @default.
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- W4286571896 date "2022-06-12" @default.
- W4286571896 modified "2023-10-18" @default.
- W4286571896 title "A 6.0mW 3.8GS/s 7b VTC/TDC-Assisted Interleaved SAR ADC with 13GHz ERBW" @default.
- W4286571896 doi "https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830329" @default.
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