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- W4288103637 abstract "Hardware Trojans have drawn the attention of academia, industry and government agencies. Effective detection mechanisms and countermeasures against such malicious designs can only be developed when there is a deep understanding of how hardware Trojans can be built in practice, in particular Trojans specifically designed to avoid detection. In this work, we present a mechanism to introduce an extremely stealthy hardware Trojan into cryptographic primitives equipped with provably-secure first-order side-channel countermeasures. Once the Trojan is triggered, the malicious design exhibits exploitable side-channel leakage, leading to successful key recovery attacks. Generally, such a Trojan requires neither addition nor removal of any logic which makes it extremely hard to detect. On ASICs, it can be inserted by subtle manipulations at the sub-transistor level and on FPGAs by changing the routing of particular signals, leading to textbf{zero} logic overhead. The underlying concept is based on modifying a securely-masked hardware implementation in such a way that running the device at a particular clock frequency violates one of its essential properties, leading to exploitable leakage. We apply our technique to a Threshold Implementation of the PRESENT block cipher realized in two different CMOS technologies, and show that triggering the Trojan makes the ASIC prototypes vulnerable." @default.
- W4288103637 created "2022-07-28" @default.
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- W4288103637 date "2019-09-22" @default.
- W4288103637 modified "2023-09-25" @default.
- W4288103637 title "Side-Channel Hardware Trojan for Provably-Secure SCA-Protected Implementations" @default.
- W4288103637 doi "https://doi.org/10.48550/arxiv.1910.00737" @default.
- W4288103637 hasPublicationYear "2019" @default.
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