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- W4289753517 abstract "The C language is getting more and more popular as a design and verification language (DVL). SystemC, ParC [1] and Cx [2] are based on C. C-models of the design and verification environment can also be generated from new DVLs (e.g. Chisel [3]) or classical DVLs such as VHDL or Verilog. The execution of these models is usually license free and presumably faster than their alternative counterparts (simulators). This paper proposes activity-dependent, ordered, cycle-accurate (AOC) C-models to speed up simulation time. It compares the results with alternative concepts. The paper also examines the execution of the AOC C-model on a multithreaded processor environment." @default.
- W4289753517 created "2022-08-04" @default.
- W4289753517 creator A5039814764 @default.
- W4289753517 date "2018-07-14" @default.
- W4289753517 modified "2023-09-27" @default.
- W4289753517 title "Deriving AOC C-Models from D&V Languages for Single- or Multi-Threaded Execution Using C or C++" @default.
- W4289753517 doi "https://doi.org/10.48550/arxiv.1807.05442" @default.
- W4289753517 hasPublicationYear "2018" @default.
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