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- W4289828075 abstract "The Secure Hash Algorithms (SHAs) are essential building blocks of modern cryptographic systems. The imple-mentation dimensions of secure hash algorithms are explored for different application scenarios. Cloud servers may favor an implementation with considerable throughput, while a compact implementation with acceptable speed and sustainable power is crucial for the Internet of Things (IoT). In this paper, we present an implementation of SHA-512 for FPGA platform based on Block RAM (BRAM) storage structure. Three implementation techniques are proposed to facilitate the usage of BRAMs as replacements for Look-Up Tables (LUTs) and Flip-Flops (FFs) to achieve a balanced FPGA utilization. Compared to other FPGA implementations of SHA-512, our design has one of the smallest slice consumption while maintaining a moderate but sufficient throughput for cryptographic applications like the post-processing of true random number generators (TRNGs)." @default.
- W4289828075 created "2022-08-05" @default.
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- W4289828075 date "2022-05-01" @default.
- W4289828075 modified "2023-09-30" @default.
- W4289828075 title "A SHA-512 Hardware Implementation Based on Block RAM Storage Structure" @default.
- W4289828075 doi "https://doi.org/10.1109/ipdpsw55747.2022.00031" @default.
- W4289828075 hasPublicationYear "2022" @default.
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