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• W4293143605 abstract "In-situ timing error detection and correction (EDAC) structure is widely adopted in timing-error resilient circuits to reduce the conservative timing guardband induced by process, voltage, and temperature (PVT) variations. However, it introduces the latch-based datapath as well as extra detection and propagation logic, therefore challenges the design-for-testability (DFT) implementation. In this article, we propose a novel DFT-compatible EDAC structure with significant signal control simplification and test-pattern complexity reduction, featuring low area and test overhead. This structure leverages a new scannable EDAC cell (SEDC) which can be configured for timing EDAC in normal mode, or for shift operations as a flip-flop in scan mode. Specifically, the proposed detection logic can be controlled succinctly in scan shift operations and then observed via the global error propagation logic with simple control signal configurations during the test. Therefore, the sophisticated test pattern generation and critical path sensitization are removed. Based on the structure, a shift-based test method is presented to cover the EDAC structure with a low test pattern complexity and test time overheads. As compared with previous works, the proposed SEDC saves 30.5% area, 16.6% power, and 20.3% delay. Besides, our test method cooperating with the proposed EDAC structure reduces <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex-math notation=LaTeX>$149times $ </tex-math></inline-formula> and <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex-math notation=LaTeX>$23times $ </tex-math></inline-formula> static and at-speed test patterns, respectively, together with <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex-math notation=LaTeX>$232times $ </tex-math></inline-formula> static test cycles, and up to <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex-math notation=LaTeX>$25times $ </tex-math></inline-formula> at-speed test cycles on average, which proves the effectiveness for DFT." @default.
• W4293143605 created "2022-08-27" @default.
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• W4293143605 date "2023-03-01" @default.
• W4293143605 modified "2023-10-05" @default.
• W4293143605 title "A DFT-Compatible <i>In-Situ</i> Timing Error Detection and Correction Structure Featuring Low Area and Test Overhead" @default.
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• W4293143605 doi "https://doi.org/10.1109/tcad.2022.3187311" @default.
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