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- W4293869128 abstract "In this paper, Schmitt trigger logic gates are designed using Dynamic Threshold MOS (DTMOS) logic that can fit subthreshold applications. In subthreshold circuits, the supply voltage is greatly reduced. When the supply voltage is scaled down, it simultaneously degrades the noise immunity of the circuit. Schmitt trigger logic manifestly being a solution to deal with noise, can be used to provide augmented noise tolerance to the circuits. To put in this logic, initially a buffer was designed and extended the concept to NAND, NOR and XNOR logic gates. The performance of Schmitt trigger logic gates using DTMOS is compared with other techniques like Conventional CMOS and Variable Threshold Voltage CMOS (VTCMOS). Besides, to know the circuit level noise tolerance, the same logic is extended to design a full adder circuit and a multiplexer circuit in which these gates are used as the logic cells. All the Schmitt trigger logic gates using DTMOS consume less power, have more noise immunity and are more energy efficient. Cadence Spectre Tool is used for simulation in 45nm technology framework." @default.
- W4293869128 created "2022-09-01" @default.
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- W4293869128 date "2022-07-01" @default.
- W4293869128 modified "2023-09-25" @default.
- W4293869128 title "Design of Noise Immune Subthreshold Circuits using Dynamic Threshold Schmitt Trigger Logic" @default.
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- W4293869128 doi "https://doi.org/10.1109/tensymp54529.2022.9864364" @default.
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