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• W4294642829 abstract "The section-carry based carry lookahead adder (SCBCLA) topology was proposed as an improved high-speed alternative to the conventional carry lookahead adder (CCLA) topology in previous works. Self-timed and FPGA-based implementations of SCBCLAs and CCLAs were considered earlier, and it was found that SCBCLAs could help in delay reduction i.e. pave the way for improved speed compared to CCLAs at the expense of some increase in area and/or power parameters. In this work, we consider semi-custom ASIC-based implementations of different variants of SCBCLAs and CCLAs to perform 32-bit dual-operand addition. Based on the simulation results for 32-bit dual-operand addition obtained by targeting a high-end 32/28nm CMOS process, it is found that an optimized SCBCLA architecture reports a 9.8% improvement in figure-of-merit (FOM) compared to an optimized CCLA architecture, where the FOM is defined as the inverse of the product of power, delay, and area. It is generally inferred from the simulations that the SCBCLA architecture could be more beneficial compared to the CCLA architecture in terms of the design metrics whilst benefitting a variety of computer arithmetic operations involving dual-operand and/or multi-operand additions. Also, it is observed that heterogeneous CLA architectures tend to fare well compared to homogeneous CLA architectures, as substantiated by the simulation results." @default.
• W4294642829 created "2022-09-05" @default.
• W4294642829 creator A5026435750 @default.
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• W4294642829 date "2016-03-25" @default.
• W4294642829 modified "2023-10-17" @default.
• W4294642829 title "ASIC-based Implementation of Synchronous Section-Carry Based Carry Lookahead Adders" @default.
• W4294642829 doi "https://doi.org/10.48550/arxiv.1603.07961" @default.
• W4294642829 hasPublicationYear "2016" @default.
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