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- W4296345552 abstract "In most distributed hard real-time scenarios, customizing a Time-Sensitive Networking (TSN) chip is critical for meeting their differentiated requirements. The open-source TSN chip aims to provide a primary reference for scenario-driven TSN chip customization. However, the design of an opensource TSN chip faces three challenges. (1) how to provide a set of basic functions for guiding the customization of the TSN chip. (2) how to provide a theoretical analysis method for evaluating the deterministic end-to-end delay and jitter. (3) how to precisely describe the data plane for enabling the development of a well-adapted control plane. To solve the above challenges, we propose FL-DPA, a data plane abstraction for the open-source TSN chip. FL-DPA consists of tables, parameters, buffers and queues. The tables in FL-DPA reflect a set of functions that satisfy the basic requirements of different TSN scenarios. The deterministic forwarding model abstracted from FL-DPA supports the theoretical analysis of end-to-end delay and jitter. Moreover, FL-DPA enables the development of a well-adapted control plane with an accurate description. The implementation details of the data plane are transparent to the control plane. To demonstrate the benefits of FL-DPA, we design an open-source TSN chip named Fenglin and build a testbed based on FPGA arrays. The experimental results show that the Fenglin chip supports mixed-critical traffic and delivers a microsecond-level determinism service." @default.
- W4296345552 created "2022-09-20" @default.
- W4296345552 creator A5040355968 @default.
- W4296345552 date "2022-06-01" @default.
- W4296345552 modified "2023-09-27" @default.
- W4296345552 title "FL-DPA: A Data Plane Abstraction Enabling Open-Source TSN Chip Design" @default.
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- W4296345552 doi "https://doi.org/10.1109/cncit56797.2022.00023" @default.
- W4296345552 hasPublicationYear "2022" @default.
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