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- W4298620008 abstract "In VLSI, memory cell is an electrical circuit that saves 1 bit of binary data and should be set to cache logic 1 and reset to cache logic 0, and the value is preserved until the set/reset functioning changes. There are two different types of memories; they are RAM and ROM memory, where RAM is used to read, write and alter the data. Here, we considering RAM because it as high-speed memory and used as primary memory. RAM is divided into two types SRAM cell and DRAM cell. SRAM is used because of its huge storage capacity and short access time; it has become a significant component in many VLSI circuits. One of the most difficulties in SRAM is designing low-power sufficient memory; power consumption is high, whereas binary cell has little amount power dissipation. Let’s look into comparative study of binary cell, SRAM cell, and SRAM cell using power-gating techniques (sleepy and stack). Here, the proposed 4*4 RAM is designed using binary cell for low-power and high-speed RAM design. The 4*4 RAM modelled and simulated using Candence Virtuoso 180 nm technology with supply of 1.8 V." @default.
- W4298620008 created "2022-10-02" @default.
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- W4298620008 date "2022-10-02" @default.
- W4298620008 modified "2023-09-25" @default.
- W4298620008 title "Designing of an Efficient 4*4 RAM Using Binary Cell" @default.
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- W4298620008 doi "https://doi.org/10.1007/978-981-19-4304-1_16" @default.
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