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- W4300504534 abstract "In this paper, we are concerned about the performance estimation of bus-based architectures assuming that the task partitioning on the processing components is already determined. Since the communication behavior is usually unpredictable due to dynamic bus requests of processing components, bus contention, and so on, simulation based approach seems inevitable for accurate performance estimation. But it is too time consuming to explore the wide design space. To overcome this serious drawback, we propose a static performance estimation method that is based on the queuing model and makes use of memory traces and task execution schedule information. We propose to use this static estimation approach to prune the design space drastically before applying a simulation-based approach. Comparison with trace-driven simulation results proves the validity of our static estimation technique." @default.
- W4300504534 created "2022-10-03" @default.
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- W4300504534 date "2003-01-01" @default.
- W4300504534 modified "2023-09-28" @default.
- W4300504534 title "Schedule-aware performance estimation of communication architecture for efficient design space exploration" @default.
- W4300504534 doi "https://doi.org/10.1145/944696.944697" @default.
- W4300504534 hasPublicationYear "2003" @default.
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