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- W4301042181 abstract "The hybrid hiding encryption algorithm, as its name implies, embraces concepts from both steganography and cryptography. In this exertion, an improved micro-architecture Field Programmable Gate Array (FPGA) implementation of this algorithm is presented. This design overcomes the observed limitations of a previously-designed micro-architecture. These observed limitations are: no exploitation of the possibility of parallel bit replacement, and the fact that the input plaintext was encrypted serially, which caused a dependency between the throughput and the nature of the used secret key. This dependency can be viewed by some as vulnerability in the security of the implemented micro-architecture. The proposed modified micro-architecture is constructed using five basic modules. These modules are; the message cache, the message alignment module, the key cache, the comparator, and at last the encryption module. In this work, we provide comprehensive simulation and implementation results. These are: the timing diagrams, the post-implementation timing and routing reports, and finally the floor plan. Moreover, a detailed comparison with other FPGA implementations is made available and discussed." @default.
- W4301042181 created "2022-10-04" @default.
- W4301042181 creator A5017610958 @default.
- W4301042181 creator A5078542829 @default.
- W4301042181 date "2007-10-25" @default.
- W4301042181 modified "2023-10-16" @default.
- W4301042181 title "An Improved FPGA Implementation of the Modified Hybrid Hiding Encryption Algorithm (MHHEA) for Data Communication Security" @default.
- W4301042181 doi "https://doi.org/10.48550/arxiv.0710.4800" @default.
- W4301042181 hasPublicationYear "2007" @default.
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