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- W4308575560 abstract "In complex processor micro-architectures with multi-cores, multiple-issue, out-of-order execution schemes, etc., it is crucial to be able to trace the program flow to design a processor hardware and software as bug-free as possible for reliability, safety and mission critical systems. Therefore, the trace-ability of a program’s execution flow is significant during processor hardware and software development cycles. In this paper, we present a hardware design and implementation of a Trace Encoder Intellectual Property (IP) that supports the multiple instructions retirement on RISC-V processor cores. Implementation follows the Efficient Trace for RISC-V processor non-Instruction Set Architecture (non-ISA) specification [1]. Moreover, a novel algorithm is introduced that is capable of capturing both single and multiple retirement of micro-operations in a multiple-issue processor core, and feeding the Trace Encoder IP with the correct micro-operation sequence through the ingress port. Results show encoding ratios down to 2.11 bits/instruction. The Trace Encoder IP has a low area overhead of 3.74%, and only consumes 3.41% of the total power w.r.t. the processor core in a commercial 28 nm CMOS process." @default.
- W4308575560 created "2022-11-12" @default.
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- W4308575560 date "2022-10-03" @default.
- W4308575560 modified "2023-09-27" @default.
- W4308575560 title "RISC-V Processor Trace Encoder with Multiple Instructions Retirement Support" @default.
- W4308575560 cites W2107072790 @default.
- W4308575560 cites W2136795172 @default.
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- W4308575560 doi "https://doi.org/10.1109/vlsi-soc54400.2022.9939596" @default.
- W4308575560 hasPublicationYear "2022" @default.
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