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- W4308651027 abstract "Signal-Integrity (SI) issues impose significant challenges to test engineers in developing a defect-free SoC design. Deep nanometer technology designs are always vulnerable to various signal-integrity issues. In complex System-on-Chip (SoC) designs, these issues are due to the ever-increasing timing delay variations in the interconnecting networks and gates. Thereby, the chip’s overall performance and power consumption are affected and contribute to a rise in the defective parts per million (DPPM). Supply noise (SN) in the power and ground networks is one factor that increase defects in an SoC. This noise can be eliminated to a great extent by modeling the SI impacts and testing the SoC design with a set of high-quality test patterns that will insure a better delay defect coverage in designs. In our work, we propose a step-by-step SN aware Automatic Test Pattern Generation (ATPG) flow by selecting a set of sensitive victim gate nets, simultaneously inducing all these victim gate nets and generating test patterns under supply noise impact. This flow uses the most effective nets for pattern generation based on the supply noise information determined from the design layout. We have developed this ATPG flow by customizing the existing scan-based techniques to capture delay defects by generating supply-noise modeled delay testable patterns. Our effective pattern generation flow is applied to ITC’99 benchmark circuits to show results." @default.
- W4308651027 created "2022-11-13" @default.
- W4308651027 creator A5038267086 @default.
- W4308651027 date "2022-10-03" @default.
- W4308651027 modified "2023-09-30" @default.
- W4308651027 title "A Signal-Integrity Aware ATPG Flow to Generate High-Quality Patterns for Testing System-on-Chip Designs" @default.
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- W4308651027 doi "https://doi.org/10.1109/vlsi-soc54400.2022.9939635" @default.
- W4308651027 hasPublicationYear "2022" @default.
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