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- W4308822766 abstract "Clock signal is a problem in contemporary synchronous circuit design. As an alternative, we have asynchronous circuits that are very promising. An essential class of asynchronous circuits due to simplified timing analysis and being robust to PVT variations (process, supply voltage, temperature) is called Quasi Delay Insensitive (QDI). However, QDI circuits have a high overhead due to signal coding, which uses delay insensitive code and excessive C elements. This paper proposes an optimized model based on basic gates and a high reduction in using C elements to implement QDI combinatorial circuits (QDI_CC), aimed at two new architectures. The proposals prove to be promising for a set of ten benchmarks comparing the proposed architectures with three architectures from the literature. Our proposal obtained an average reduction of up to 51.9% in the estimated number of transistors." @default.
- W4308822766 created "2022-11-16" @default.
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- W4308822766 date "2022-10-11" @default.
- W4308822766 modified "2023-09-30" @default.
- W4308822766 title "Synthesis of QDI Combinational Circuits Implemented on Optimized Model" @default.
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- W4308822766 doi "https://doi.org/10.1109/etcm56276.2022.9935742" @default.
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