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- W4310521396 abstract "Paralleling connection of silicon carbide (SiC) MOSFETs is often used in high power industrial and automotive power conversion application. However, asymmetric power or driver loop can result in dynamic or static problem and even device failure. This paper comprehensively analyzes the mechanism of gate-source voltage <tex xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>$(v_{text{gs}})$</tex> oscillation during SiC MOSFET turn-on caused by the combination effects of power loop mismatch and feedback from SiC MOSFET parasitic Miller capacitor to gate-source voltage, further, discusses the influences of hardware parameters on this phenomenon and how to reduce. In addition, the simulation analysis in PSpice validated the discussed oscillation mechanism and hardware designing guideline on the oscillation reduction. Finally, experimental verification based on paralleled SiC MOSFET modules are given." @default.
- W4310521396 created "2022-12-11" @default.
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- W4310521396 date "2022-10-09" @default.
- W4310521396 modified "2023-10-03" @default.
- W4310521396 title "Analysis and Reduction of Turn-on Gate-source Voltage Oscillation on Paralleled SiC MOSFETs Application" @default.
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- W4310521396 doi "https://doi.org/10.1109/ecce50734.2022.9947878" @default.
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