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- W4310584084 abstract "Aiming at the problems of long operation time and poor flexibility of embedded processor, this paper proposes a structure of configurable execution unit based on RISC-V extended instruction set for computing granularity. The structure sets up basic parallel computing units and configuration registers, which can realize a large number of parallel operations such as multiplication, addition, or higher abstractions similar to convolutional neural networks by software configuration. This paper completed the design of this structure and integrated it into a four-stage pipelined RISC-V processor. The white blood cell images collected by lensless system are used to test various image algorithms. The experimental results show that the processor speed designed in this paper is 5.95 times to 22.21 times higher than that of the ordinary pipeline processor, and the number of instructions required is reduced by 1.16 times to 7.49 times. Therefore, the processor has a certain improvement in processing speed and flexibility, which is of great significance for the implementation of various algorithms in embedded systems." @default.
- W4310584084 created "2022-12-12" @default.
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- W4310584084 date "2022-10-25" @default.
- W4310584084 modified "2023-10-16" @default.
- W4310584084 title "Design of computing granularity configurable processor based on RISC-V extended instruction" @default.
- W4310584084 doi "https://doi.org/10.1109/icsict55466.2022.9963166" @default.
- W4310584084 hasPublicationYear "2022" @default.
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