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- W4310584433 abstract "Binarized Neural Network (BNN) is an ultra-reduced-size version of Convolutional Neural Network (CNN), with weights and activations reduced to 1-bit, which largely decreases parameters of a CNN. The convolutional operation in CNN can be transformed into XNOR-popcount operation in BNN. FPGA is an appealing platform to implement BNN. In order to increase popcount computation density on FPGA, FPGA logic cell needs to modify. Compare to previous modifications, we propose two improvements. First, we propose area-saving full adder reuse technique, the full adder can propagate SUM or CARRY. Second, modified logic cell can efficiently implement 6:3 compressor which decreases number of full adders in popcount computation. compared to previous modifications, our proposed improvements decrease FPGA logic cell area by 1.65X—2.48X, and critical path doesn’t deteriorate. Improvements don’t add any port to original logic cell which doesn’t affect routing. Compared with original logic cell to implement 6:3 compressor, we reduce 3X logic cells." @default.
- W4310584433 created "2022-12-12" @default.
- W4310584433 creator A5063658433 @default.
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- W4310584433 date "2022-10-25" @default.
- W4310584433 modified "2023-10-16" @default.
- W4310584433 title "FPGA Logic Cell Improvements for Popcount Computation in BNN" @default.
- W4310584433 cites W1523051745 @default.
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- W4310584433 doi "https://doi.org/10.1109/icsict55466.2022.9963213" @default.
- W4310584433 hasPublicationYear "2022" @default.
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