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- W4310607304 abstract "This paper presents a N-type flipped voltage follower (FVF) based low-dropout (LDO) regulator to provide a clean supply for analog-mixed signal blocks. The FVF LDO has a high-speed inner loop to improve the power supple rejection at mid frequency. In order to achieve low noise, the sample-and-hold noise filter and chopper stability amplifier are designed to reduce the thermal noise and flicker noise. This work is designed and simulated in 0.1Sum CMOS process with 5V VIN and 2. 5V VOUT. The integrated output noise of the LDO in the 10Hz to 100kHz is 6.77uV <inf xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>RMS</inf> and the power supply rejection is S5.05dB at 1MHz." @default.
- W4310607304 created "2022-12-12" @default.
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- W4310607304 date "2022-11-04" @default.
- W4310607304 modified "2023-10-18" @default.
- W4310607304 title "A Low Noise High PSR LDO Based on N-type Flipped Voltage Follower" @default.
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- W4310607304 doi "https://doi.org/10.1109/peac56338.2022.9959400" @default.
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