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- W4310608679 abstract "This paper presents a fully synthesizable injection locked phase-locked loop (PLL), with a dual-DCO frequency tracking. The design has been fabricated in 55-nm CMOS and the layout is realized completely by digital flows. The proposed PLL covers a 0.2-to-1.2-GHz tuning range, achieving an absolute rms jitter (integrated from 100kHz to 100MHz) of 3.2ps at 4.3-mW power consumption, with a corresponding jitter-power figure of merit (FoM) of -224dB and the occupied core area is only 0.0225 mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> ." @default.
- W4310608679 created "2022-12-13" @default.
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- W4310608679 date "2022-10-28" @default.
- W4310608679 modified "2023-10-18" @default.
- W4310608679 title "A Fully Synthesizable Injection Locked PLL with Dual-DCO Frequency Tracking in 55nm CMOS" @default.
- W4310608679 doi "https://doi.org/10.1109/icta56932.2022.9962990" @default.
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